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X9470
Data Sheet March 8, 2005 FN8204.0
PRELIMINARY
RF Power Amplifier (PA) Bias Controller
FEATURES * Programmable Bias Controller IC for Class A and AB LDMOS Power Amplifiers * Adaptive System on Chip Solution * Bias Current Calibration to better than 4% using Reference Trim DCP * Automatic Bias Point Tracking and Calibration -- IDQ Sensing and Tracking --Programmable Instrumentation Amplifier to Scale Wide Range of IDQ --Programmable Gate Bias Driver --All Programmable settings are Nonvolatile --All Settings Recalled at Power-up. * 28V Maximum VDD * 2 Wire Interface for Programming Bias Setting and Optimizing IDQ Set Point * Bias Level Comparator * Shutdown Control pin for PA Signal * Slave address to allow for multiple devices * 24-pin TSSOP Package * Applications: Cellular Base Stations (GSM, UMTS, CDMA, EDGE), TDD applications, Pointto-multipoint, and other RF power transmission systems TYPICAL APPLICATION
INC/DEC A2 A1
Comparator
DESCRIPTION The Intersil X9470 RF PA Bias Controller contains all of the necessary analog components to sense the PA drain current through an external sense resistor and automatically control the gate bias voltage of an LDMOS PA. The external sense resistor voltage is amplified by an instrumentation amplifier and the output of the amplifier along with an external reference voltage is fed to the inputs of a comparator. The comparator output indicates which direction the LDMOS gate bias voltage will move in the next calibration cycle. System calibration is accomplished by enabling the X9470 and providing a clock to the SCL pin. The LDMOS drain current can be maintained constant over temperature and aging changes by periodic calibration. The VOUT pin can be used to monitor the average power by tracking the drain current. Up to eight X9470 or additional Intersil Digital Potentiometers can be controlled via a twowire serial bus.
RWREF RHREF RLREF RREF VREF
AGND
VOUT
V+
VDD VSENSE+ V VSENSE- CBULK RSENSE
A0
VP I2C interface Vbias control + - VBIAS (Unbuffered)
Control & Status Registers
Instrumentation Amplifier VREF control RBIAS VBIAS FILTER RF out choke
SDA SCL
RF PA in
Matching RF Impedance
EEPROM VCC VSS CS
RHBIAS RWBIAS RLBIAS
SHDN
Class A Example
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9470
PIN CONFIGURATION
TSSOP Vsense+ RHREF RLREF RWREF AGND VSS CS SCL SDA RHBIAS RWBIAS RLBIAS 1 2 3 4 5 6 7 8 9 10 11 12 X9470 24 23 22 21 20 19 18 17 16 15 14 13 VsenseSHDN INC/DEC VOUT V+ VCC VCC VBIAS VSS A2 A1 A0
ORDERING INFORMATION
Part Number Temperature Range Package
X9470V24I
-40C TO 85C
24-Lead TSSOP
PIN DESCRIPTIONS
TSSOP pin Symbol
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
VSENSE+ RHREF RLREF RWREF AGND VSS CS SCL SDA RHBIAS RWBIAS RLBIAS A0 A1 A2 VSS VBIAS VCC VCC V+ VOUT INC/DEC SHDN VSENSE-
Brief Description Positive sense voltage input terminal Upper Terminal of Potentiometer, called the RREF potentiometer. The voltage applied to this pin will determine the upper voltage limit of the adjustment for the Up/Down threshold of the comparator. Lower Terminal of Potentiometer, called the RREF potentiometer. The voltage applied to this pin will determine the lower voltage limit of the adjustment for the Up/Down threshold of the comparator. Wiper Terminal of Potentiometer, called the RREF potentiometer. The voltage on this pin will be the threshold for the Up/Down comparator. Also referred to as the VREF of the comparator. Analog ground to allow single point grounding external to the package to minimize digital noise. System (Digital) Ground Reference Chip Select. This input enables bias calibration adjustments to the RBIAS potentiometer. CMOS input with internal pull-down. Dual function. Function 1: The increment control input. Increments or decrements the RBIAS potentiometer. Function 2: Serial Data Clock Input. Requires external pull-up. Serial Data Input. Bi-directional 2-wire interface. Requires external pull-up. Upper Terminal of Potentiometer, called the RBIAS potentiometer. The voltage applied to this pin will determine the upper limit of the bias voltage to the PA (or VBIAS pin). Wiper Terminal of Potentiometer, called the RBIAS potentiometer. This voltage is the equivalent to the unbuffered voltage that will appear at the VBIAS pin. Lower Terminal of Potentiometer, called the RBIAS potentiometer. The voltage applied to this pin will determine the lower limit of the bias voltage to the PA (or VBIAS pin). External address pin which allows for a hardware slave address selection of this device. This pin has an internal pull-down. External address pin which allows for a hardware slave address selection of this device. This pin has an internal pull-down. External address pin which allows for a hardware slave address selection of this device. This pin has an internal pull-down. System (Digital) Ground Reference This is the bias output voltage pin and is used to drive the filter network to the PA gate. System (Digital) Supply Voltage System (Digital) Supply Voltage Positive voltage supply for the instrumentation amplifier and other analog circuits. Instrumentation Amplifier output that is 20x or 50x the voltage across the Rsense pins. Status output that indicates the state of the comparator. When this pin is HIGH, the RBIAS potentiometer will increment; when the pin is LOW, the RBIAS potentiometer will decrement. This pin is open drain and requires external resistor pull-up. Shutdown the output op amp. When SHDN is active (HIGH), the VBIAS pin is pulled LOW. Negative sense voltage Input terminal
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ABSOLUTE MAXIMUM RATINGS* Voltage on V+ (referenced to AGND) ...................... 7V Voltage on VCC (reference to VSS) ........................ 7V Voltage on all RH, RW, RL pins (reference to AGND): ........................................... 7V Voltage on Vsense+ or Vsense- (reference to AGRND).......................... 30V Voltage on SDA, CS, SCL, SHDN (reference to AGND) ............... -0.3V to (Vcc + 0.3V) Current into Output Pin:.......................................... 5mA Continuous Power Dissipation: ....................... 500mW Operating Temperature range:.............. -40C to +85C Junction Temperature: ..........................................150C Storage Temperature ........................ -65C to +150C Lead Temperature (Soldering, 10 seconds): ..... 300C *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS INSTRUMENTATION AMPLIFIER Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40C to +85C, unless otherwise noted.) Limits Symbol
VIN
(10)
Parameter
Common Mode Input Voltage on VSENSE+ and VSENSE- pins Gain from VSENSE to VOUT(2) Gain from VSENSE to VOUT(2) Differential voltage sense range between VSENSE+ and VSENSE- for gain 1 Differential voltage sense range between VSENSE+ and VSENSE- for gain 2 Input Offset Voltage Gain 1 Error Gain = 20 (4) Gain 2 Error Gain = 50 (4) Total Error, Gain 1 Gain = 20 (5)
Min. Typ. Max. Units
20 20 50 60 40 0.5 1.5 1.5 -6 1.5 10 6 90 60 28 V V/V V/V mV mV mV % % % % 6 % % % V/S
Test Conditions/Notes
Gain 1 Gain 2 VRANGE1 VRANGE2 VOS Av1 Av2 Avt1
Measured with Status Register bit SR0 = 0 Measured with Status Register bit SR0 = 1 Gain = 20 Gain = 50 VSENSE = 40mV to 90mV TA = 25C VSENSE = 60mV to 90mV TA = 25 to 85C, Gain = 20 VSENSE = 40mV to 60mV TA = 25 to 85C, Gain = 50 VSENSE = 60mV to 90mV TA = 85C, Gain = 20 VSENSE = 60mV to 90mV TA = 25 to 85C, Gain = 20 VSENSE = 40mV to 60mV TA = 85C, Gain = 50 VSENSE = 40mV to 60mV TA = 25 to 85C, Gain = 50 Avt1 or Avt2 VSENSE = 20mV step, Cout = 10pF Measured at VOUT(1,3)
Avt2
Total Error, Gain 2 Gain = 50 (5)
-6
1.5 10
At SR(10)
Long Term Drift Slew Rate of Instrumentation Amp
2 0.2
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ELECTRICAL CHARACTERISTICS INSTRUMENTATION AMPLIFIER (CONTINUED) Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40C to +85C, unless otherwise noted.) Limits Symbol
Tsettle(10)
Parameter
Setting time of Instrumentation Amp
Min. Typ. Max. Units
5.0 S
Test Conditions/Notes
VSENSE = 20mV step, Cout = 10pF, settling to 1% of final value Measured at VOUT(1,3) For both Gain 1 and Gain 2 For both Gain 1 and Gain 2 Gain = 20 Gain = 50 Gain = 20 TA = 25C Each Input
CMRR PSRR VOUT Range VOUT Noise(10) IVSENSE(10) CVSENSE(10)
Common Mode Rejection Ratio Power Supply Rejection Ratio VOUT Voltage Swing VOUT Voltage Noise, rms VSENSE+, VSENSE- Input Bias Current VSENSE+, VSENSE- Input Capacitance 0.3 0.3
40 55 1.8 3.0 3 250 10
dB dB V V mV A pF
COMPARATOR Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40C to +85C, unless otherwise noted.) Limits Symbol
VOL Io(10) Vos(10) Tpd(10)
Parameter
Output Voltage Low on the INC/DEC pin Output sink Current Input Hysteresis Response Time for propagation delay
Min.
Typ.
Max. Units
0.4 3 V mA mV S
Test Conditions/Notes
IOL = 1mA
INC/DEC pin, open drain
Vcc = 5 V
20 2
INC/DEC pin with 2k pull up
VREF DCP CIRCUIT BLOCK Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40C to +85C, unless otherwise noted.) Limits Symbol
RTOTAL VRH VRL VRW
Parameter
End to End Resistance Number Taps or Positions RHREF Terminal Voltage RLREF Terminal Voltage RWREF Terminal Voltage Power Rating(10) Linearity(6) Resolution(10) Absolute
Min.
8 AGND AGND AGND
Typ.
10
Max.
12 64 V+ V+ V+
Units
k V V V mW %
Test Conditions/Notes
AGND = 0V AGND = 0V AGND = 0V RTOTAL =10k
2.5 1.6 -0.2 -0.2 +0.2 +0.2
MI(8) MI(8)
Relative Linearity(7)
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VREF DCP CIRCUIT BLOCK Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40C to +85C, unless otherwise noted.) Limits Symbol Parameter
RTOTAL Temperature CIN
(10)
Min.
-20
Typ.
300
Max.
+20
Units
ppm/C ppm/C pF
Test Conditions/Notes
Coefficient(10) Coefficient(10)
Ratiometric Temperature
Potentiometer Capacitances on RHREF and RLREF
10
BIAS ADJUSTMENT DCP CIRCUIT BLOCK Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40C to +85C, unless otherwise noted.) Limits Symbol
RTOTAL VRH VRL VRW
Parameter
End to End Resistance Variation Number Taps or Positions Voltage at the RHBIAS Terminal Voltage Voltage at the RLBIAS Terminal Voltage Voltage at the RWBIAS Terminal Voltage Power Rating(10) Resolution(10) Absolute Linearity(6) Relative Linearity(7) RTOTAL Temperature Coefficient(10) Coefficient(10) Ratiometric Temperature
Min.
8 AGND AGND AGND
Typ.
10
Max.
12 256 V+ V+ V+
Units
k V V V mW %
Test Conditions/Notes
with 20% variation AGND = 0V AGND = 0V AGND = 0V RTOTAL =10 K
2.5 0.4 -1.0 -1.0 300 -50 10 50 +1.0 +1.0
MI(8) MI(8) ppm/C ppm/C pF
CIN
(10)
Potentiometer Capacitances on RHBIAS and RLBIAS
VBIAS OUTPUT VOLTAGE FOLLOWER Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40C to +85C, unless otherwise noted.) Limits Symbol
VOS VOSDRIFT(10) SR VBIAS TS(10) tSHDN PSRR
Parameter
Input Offset Voltage Offset Voltage Temperature Coefficient Output Slew Rate on VBIAS Voltage Output Swing Settling Time Time for SHDN pin (delay) valid Power Supply Rejection Ratio
Min.
Typ.
10 10 0.5
Max.
Units
mV V/C V/S
Test Conditions/Notes
TA = -40 to +85C RL = 10k, 1nF, VBIAS = 20mV IOUT = 10mA Final value 1%, RL = 10k, 1nF, VBIAS = 20mV VCC supply VCC = 4.75 to 5.25V
1.5 2 0.1 45 55
VCC - 0.5
V s
1.0
s dB
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VBIAS OUTPUT VOLTAGE FOLLOWER Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40C to +85C, unless otherwise noted.) Limits Symbol
CL(10) CIN(10) ROUT(10)
Parameter
Input Voltage Range Load Capacitance Capacitances on Shutdown Pin Output Impedance
Min.
1.5
Typ.
1 10 3
Max.
VCC - 0.5
Units
V nF pF
Test Conditions/Notes
at 5MHz, 1nF load
D.C. OPERATING CHARACTERISTICS Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40C to +85C, unless otherwise noted.) Limits Symbol
ICC1(9) ICC2(9)(10) ISB(9)
Parameter
V+ Active Current VCC Active Current Standby Supply Current (VCC, V+) CS, SDA, SCL, SHDN RH, RL, RW, INC/DEC VOUT, Input Leakage CS, SDA, SCL, SHDN, A0, A1, A2 HIGH Voltage CS, SDA, SCL, SHDN, A0, A1, A2 LOW Voltage CS, SDA, SCL, SHDN, A0, A1, A2 Capacitance
Min.
Typ.
1 5 1.5
Max.
3 25
Units
mA mA mA
Test Conditions CS = VCC - 0.3V, and SCL @ max. tCYC, SDA = VCC 0.3V, SHDN inactive CS = VIL, and SCL inactive (no clock), SDA =VIL, SHDN active
VIN = VSS to VCC
ILI VIH(10) VIL(10) CIN(10)
-10 VCC x 0.7 -0.5 10
10 VCC + 0.5 VCC x 0.3
A V V pF
VCC = 5V, VIN = VSS, TA = 25C, f = 1MHz
Notes: (1) VOUT is a high impedance output intended for light loads only. (2) Gain at VOUT is set to 20 by default. (3) Value given is for VOUT. The VBIAS output will depend on the VBIAS potentiometer which is initially loaded with a zero value, then followed by the loading of the final value from E2 memory. (4) Gain Error excludes the contribution of the input offset voltage error. (5) Total Error includes the contributions of gain error and input offset voltage error. (6) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage = (Vw(n)(actual) - Vw(n)(expected)) (7) Relative Linearity is a measure of the error in step size between taps = VW(n+1) - [Vw(n) + Ml] (8) 1 Ml = Minimum Increment = RTOT/63 or RTOT/255. (9) Typical values are for TA = 25C and nominal supply voltage, VCC = 5V. (10) This parameter is not 100% tested.
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BIAS ADJUSTMENT CIRCUIT BLOCK A.C. OPERATING CHARACTERISTICS Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; TA = -40C to +85C, unless otherwise noted.) Limits Symbol
tCl tlD tlL tlH tlC
(10)
Parameter CS to SCL Setup
Vsense Change to INC/DEC Change SCL LOW Period SCL HIGH Period SCL Inactive to CS Inactive SCL to VBIAS Change SCL Cycle Time SCL Input Rise and Fall Time
Min.
100
Typ.(9)
5
Max.
Units
ns s s s ns
1.5 1.5 100 3 3 500
tIW(10)(11) tCYC tR, tF
(10)
s s ns
A.C. TIMING CS
tCYC tCI tIL tIH tIC 90% 90% 10% tID tF tR
SCL
INC/DEC
tIW VBIAS
(Vsense+ - Vsense-)
Note:
(11) MI in the A.C. timing diagram refers to the minimum incremental change in the VBIAS output due to a change in the wiper position.
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AC SPECIFICATIONS Symbol
fSCL tIN
(10) (10) (10)
Parameter
SCL Clock Frequency Pulse width Suppression Time at inputs SCL LOW to SDA Data Out Valid Time the bus must be free before a new transmission can start Clock LOW Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time Data Output Hold Time SDA and SCL Rise Time SDA and SCL Fall Time Capacitive load for each bus line 20
Min.
0 50 0.1 1.3 1.3 0.6 0.6 0.6 200 200 0.6 50 +.1Cb(12)
Max.
400 0.9
Unit
kHz ns s s s s s s ns ns s ns
tAA
tBUF
tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH tR
(10) (10)
300 300 400
ns ns pF
tF(10) Cb(10)
Note:
20 +.1Cb(12)
(12) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS Bus Timing
tF SCL tSU:ST SDA IN tHD:STA tSU:DAT tHD:DAT tSU:STO tHIGH tLOW tR
tAA SDA OUT
tDH
tBUF
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK tWC Stop Condition Start Condition
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Power-up Timing Symbol
tr VCC
Note:
(10)
Parameter
VCC Power-up rate
Min.
0.2
Max.
50
Unit
V/ms
Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are not 100% tested. Proper recall of stored wiper setting requires a VCC power-up ramp that is monotonic and with noise or glitches < 100mV. It is important to correctly sequence voltages in an LDMOS amplifier circuit. For the X9470 typical application, the VCC, then V+ pins should be powered before the VDD of the LDMOS to prevent LDMOS damage. Under no circumstances should the VDD be applied to the LDMOS device before VCC and V+ are applied to the X9470.
DCP Default Power-up Tap Positions (shipped from factory)
VREF DCP Bias Adjust DCP 0 0
Nonvolatile Write Cycle Timing Symbol
tWC
Note:
(10)
Parameter
Write Cycle Time
Min.
Typ.(1)
5
Max.
10
Unit
ms
tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
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DETAILED PIN DESCRIPTIONS Supply Pins Digital Supplies VCC, VSS The positive power supply and ground for the DCP digital control sections. VSS is normally tied to digital ground. The X9470 is provided with separate digital and analog power supply pins to better isolate digital noise from the analog section. Analog Supplies V+, AGND The positive analog supply and ground for the Instrumentation Amplifier (IA). The analog supply ground is kept separate to allow an external single point connection. V+ can be a separate supply voltage from VCC, or VCC can be filtered before connection to V+. Bias Adjustment Circuit Block Pins RHBIAS , RLBIAS , and RWBIAS for VBIAS Adjustments. These pins are the connections to a Intersil Digitally Controlled Potentiometer (XDCPTM) or RBIAS potentiometer. RHBIAS is connected to the most positive reference, and the RLBIAS is connected to the least positive reference voltage. The potentiometer has a resolution of 256-taps and typical RTOTAL of 10k. So for example, to provide 4mV resolution, the voltage difference applied to the RHBIAS and RLBIAS pins must be 1.024V. The RWBIAS value can be stored in nonvolatile memory and recalled upon power-up. Serial Clock (SCL). This is a dual function input pin. The state of the CS pin determines the functionality. Function 1: SCL is a negative edge-triggered control pin of the RBIAS potentiometer. Toggling SCL will either increment or decrement the wiper in the direction indicated by the logic level on the INC/DEC pin. CS must be high for this function. Function 2: SCL is the serial bus clock for serial bus interface. CS must be low for this function. Chip Select (CS). Calibration Enable. The CS input is the enable bias adjustments. When the CS is HIGH (enabled) and a SCL pulse is present, the wiper position on the RBIAS potentiometer will automatically update with either an increment or decrement of one tap position according to INC/DEC signal from the comparator. When CS is LOW (disabled), the wiper counter of the XDCP will hold the last wiper position until CS is enabled again and the wiper position is updated. INC/DEC Monitor Pin The Up or Down Monitor pin (INC/DEC) indicates the state of the comparator. This signal indicates that the Instrumentation Amplifier output voltage is higher or lower than the voltage level set by the RWREF pin. The output is used to indicate the direction that the gate bias voltage needs to move to reach the target bias voltage. Sense and Scale Block Pins VSENSE+ and VSENSEThese are the input pins to the IA circuit. These pins are used to determine the change in voltage across the the external drain sense resistor of an RF power amplifier. RHREF , RLREF, and RWREF. PA Bias Set Point. The PA Bias reference voltage is controlled by a 64tap (10k typical RTOTAL) potentiometer, called the RREF potentiometer. The voltages applied to RHREF and RLREF will determine the range of adjustment of the reference voltage level (VREF) for the Comparator. The resolution of the comparator reference is the difference of the voltages applied to RHREF and RLREF divided by 63. The position of the wiper (RWREF) is controlled via serial bus. The RWREF value can be stored in non-volatile memory and recalled upon power-up. RWREF is also an input signal used as a scaling voltage (VREF) to set the appropriate IDQ of an RF power amplifier. VREF can be derived from an external voltage divider or from a baseband processor or similar microcontroller. VREF can be set permanently or changed dynamically using the potentiometer for various PA operating points. VOUT This pin is the output of the IA, which reflects a 20x or 50x gain of the input signal (voltage across the Vsense pins). It can be used to indicate the magnitude of the drain current envelope when RF is present.
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Output Block Pins VBIAS The VBIAS is the gate bias voltage output. It is buffered with a unity gain amplifier and is capable of driving 1nF (typical) capacitive loads. This pin is intended to be connected through an RF filter to the gate of an LDMOS power transistor. The voltage of VBIAS is determined by the XDCP's value of the RBIAS resistor. Other Pins SHDN SHDN is an input pin that is used to shutdown the VBIAS output voltage follower. When the SHDN pin is HIGH, the VBIAS pin is pulled to VSS. When the device is shutdown, the current RBIAS wiper position will be maintained in the wiper counter register. When shutdown is disabled, the wiper returns to the same wiper position before shutdown was invoked. Note that when the device is taken out of shutdown mode (SHDN goes from HIGH to LOW), the CS input must be cycled once to enable calibration. SDA Serial bus data input/output. Bi-directional. External pullup is required. A0, A1, A2 Serial bus slave address pins. These pins are used to defined a hardware slave address. This will allow up to 8 of the X9470's to be shared on one two-wire bus. These are useful if several X9470's are used to control the bias voltages of several LDMOS Power Transistors in a single application. Default hardware slave address is "000" if left unconnected due to internal pull-down resistor. TYPICAL APPLICATION The X9470 can be used along with a microprocessor and transmit control chips to control and coordinate FET biasing (see Figure 1). The CS, SCL, and SDA signals are required to control the X9470 Bias Adjustment Circuit Block. An internal RWREF voltage is provided via a programmable voltage divider between the RHREF and RLREF pins and is used to set the voltage reference of the comparator. The shutdown (SHDN) and bias voltage indicators (INC/DEC) are additional functions that offer FET control, monitoring, and protection. Typically, the closed loop setup of the X9470 allows for final calibration of a power amplifier at production test. The CS and SCL pins are used to perform this calibration function. Once in a base station, the amplifier can then be re-calibrated any time that there is no RF signal present. The bias setting block can also be used open loop to adjust gate bias or can be shutdown using the SHDN pin. The sense and scale block can be used for amplifier power monitoring diagnostics as well. The range of the drain bias current operating point of the LDMOS FET is set by an external reference across the reference potentiometer. The wiper of the potentiometer sets the trip point for comparison with VP , the amplified voltage across RSENSE, the drain resistor. The output of the comparator causes the RBIAS potentiometer to increment or decrement automatically on the next SCL clock cycle. This RBIAS potentiometer is configured as a voltage divider with a buffered wiper output which drives the gate voltage of an external LDMOS FET. Once the optimum bias point is reached, the RBIAS value is latched into a wiper counter register. Again, the VBIAS gate voltage can be updated continuously or periodically depending on the system requirements. Both terminals of the RBIAS potentiometer are accessible and can be driven by external reference voltages to achieve a desired IDQ vs. gate voltage resolution, as well as supporting temperature compensation circuitry. In summary, the X9470 provides full flexibility on setting the operating bias point and range of an external RF power amplifier for GSM, EDGE, UMTS, CDMA or other similar applications.
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Figure 1. Typical Application
INC/DEC A2 A1
Comparator
RWREF RHREF RLREF RREF VREF
AGND
VOUT
V+
VDD VSENSE+ V VSENSE- CBULK RSENSE
A0
VP I2C interface Vbias control + - VBIAS (Unbuffered)
Control & Status Registers
Instrumentation Amplifier VREF control RBIAS VBIAS FILTER RF out choke
SDA SCL
RF PA in
Matching RF Impedance
EEPROM VCC VSS CS
RHBIAS RWBIAS RLBIAS
SHDN
Class A Example
X9470 FUNCTIONAL DESCRIPTION This section provides detail description of the following: - Sense and Scale Block Description - Bias Adjustment Control Block Description - Output Block Description - Bias Adjustment and Storage Description SENSE AND SCALE BLOCK The Sense and Scale Circuit Block (Figure 2) implements an instrumentation amplifier whose inputs (VSENSE+ and VSENSE-) are across an external sense resistor in the drain circuit of an RF Power FET. VSENSE+ is connected to VDD, the drain voltage source for the RF power FET, and VSENSE- pin is connected to the other end the external sense resistor. An internal instrumentation amplifier (IA) will sense the V and amplify it by a gain factor of K1 (see Equation 1). The resulting output is compared with VREF at the comparator. VREF can be a fixed reference voltage or adjusted by using the 64-tap digital potentiometer. The output of the comparator is used to increment or decrement the RBIAS potentiometer in the Bias Adjustment Circuit Block. The gain factor K1 is designed such that the Sense and Scale Block will set the Bias Adjustment Circuit Block to operate in a given voltage range (mV) vs. drain current adjustment (mA). VREF (1) IDQ K1 * RSENSE K1 is fixed 50x for the internal comparator input.
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The output of the IA is also available at the pin Vout to enable drain current monitoring. The gain at Vout is fixed at a factor of K2, lower than K1 so that high IDQ currents will not cause saturation of the Vout signal. The equation for Vout is given as: V = IDQ * RSENSE VOUT = K2 * V K2 is fixed to 20x for the Vout pin BIAS ADJUSTMENT CIRCUIT BLOCK There are three sections of this block (Figure 3): the input control, counter and decode section (1), the resistor array (2); and the non-volatile register (3). The input control section operates just like an up/down counter. The input of the counter is driven from the output of the comparator in the Sense and Scale Block and is clocked by the SCL signal. The output of this counter is decoded to select one of the taps of a 256tap digital potentiometer.
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Figure 2. Sense and Scale Block Diagram
VDD INC/DEC RWREF RHREF RLREF VOUT Cint~2pF 10% VSENSE+ RSENSE VSENSE- IDQ
}
V
VREF
10k 64-tap
K2 = 20X ~1k Precision I-Amp K1 = 50X
choke
RF PA Out
Comparator INC/DEC
Vgate
RF PA in
The wiper of the digital potentiometer acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches in the potentiometer operate in a "make before break" mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (SCL to RWBIAS change). When the device is powered-up, the X9470 will load the last saved value from the non-volatile memory into the WCR. Note that the current wiper position can be saved into non-volatile memory register by using the SCL and CS pins as shown in Figure 4. Important note: the factory setting of the wiper counter register is the ZERO-position (0 of 255 taps). This is the default wiper position. Bias Adjustment Block Instructions and Programming. The SCL, INC/DEC (internal signal) and CS inputs control the movement of the wiper along the resistor array. (See Table 1) With CS set HIGH, the device is selected and enabled to respond to the INC/DEC and SCL inputs. HIGH to LOW transitions on SCL will increment or decrement RBIAS (depending on the state of the INC/DEC input). The INC/DEC input is derived from the output of the comparator of the Sense and Scale Block.
Storing Bias Resistor Values in Memory. Wiper values are stored to VOLATILE memory automatically when CS is HIGH and INC/DEC either transitions from HIGH to LOW or from LOW to HIGH. Wiper values are stored to NON-VOLATILE memory during Byte Write or as described in the following section. Table 1. Mode Selection SDA
H H H
CS*
H H H
SCL
INC / DEC
H L
Mode
VBIAS is incremented one tap position. VBIAS is decremented one tap position. Lock Wiper Position. Save to volatile memory. (BiasLockTM) Open Loop.
X or
X
L
X
X
* When coming out of shutdown, the CS pin must be cycled once before bias adjustment is enabled.
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Figure 3. Bias Adjustment Block Diagram
Gate Bias Op Amp - RWBIAS RHBIAS RLBIAS VBIAS (unbuffered) 2 RBIAS 10k 256-tap SHDN +
VBIAS to LDMOS gate
XDCP Memory and Control
Legend External pin/signal Internal node/signal 3
WCR (Rbias) Bias Register non-volatile Power-On Recall (POR)
INC/DEC is logic HIGH or LOW from Sense/Scale Block and is used to increment or decrement the Rbias resistor (XDCP) to adjust the gate voltage.
1 INC/DEC
Note: 1) WCR = Wiper Control Register
SCL CS
INC
U/D CS
NON-VOLATILE STORE OF THE BIAS POSITION The following procedure will store the values for the Rref and Rbias wiper positions in Non-Volatile memory. This sequence is intended to be performed after a BiasLock calibration sequence to simplify storage. If BiasLock has not been achieved, then the Rbias wiper position may change when the CS pin is brought high and SCL begins clocking. See Figure 4 for the actual sequence. 1. Set the WEL bit with a write command (02h to register 0Fh) 2. Peform a calibration and achieve BiasLock. Leave CS pin high. 3. Write the address byte only (START, followed by device/slave address and a 0 for a write, see page 19). 4. Perform a STOP command. 5. With SCL still low, bring the CS low. The falling edge of the CS will initiate the NV write. The WEL bit may be reset afterwards to prevent further NV writes. INC/DEC FUNCTION The INC/DEC pin is an open-drain logic output that tracks the activity of the increment/decrement comparator. A logic HIGH at INC/DEC indicates that the IDQ did not rise up to the desired setting indicated by VREF while a logic LOW at the INC/DEC pin indicates that the IDQ is higher than the desired setting.
INC/DEC is used as an internal control signal as well. As an example, when INC/DEC is LOW, the Bias Adjustment Circuit Block will start to move the Rbias resistor wiper towards the RLBIAS terminal end when CS is HIGH and SCL is clocking. Consequently, the VBIAS voltage will decrease, and the IDQ decreases to meet the desired VREF setting. The INC/DEC signal can also be used to detect a damaged RF power FET. For instance, If INC/DEC stays HIGH during and after a calibration sequence it may indicate that the RF power FET has failed. This indicator can also be used with a level sense on the VOUT pin to perform diagnostics. SHUTDOWN MECHANISM This hardware control shutdown pin (SHDN) will pull the voltage of VBIAS to VSS with an internal pull down resistor. When shutdown is disabled (VBIAS is active when SHDN is LOW), the VBIAS voltage will move to the previous desired bias voltage. It will take less than a microsecond to enable the internal output buffer depending on the loading condition at the VBIAS pin. OUTPUT (VBIAS) VBIAS is a buffered output of RWBIAS (wiper output). It can deliver a high current for driving up to typically 1nF capacitive loading with stable performance and fast settling time.
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A single pole filter should be placed in between the VBIAS output and the RF input signal to isolate any high frequency noise. Figure 4. Non-Volatile Store of the Bias Position
Calibration Set and Bias Lock Address Byte Stop Initiates high voltage write cycle 5 SCL
CS
Set WEL bit 1
2
3
4
SDA
RBIAS non-volatile register
tWR Stored in Non-volatile memory Non-volatile Write of RBIAS and RREF value Using SDA, SCL and CS pins
X9470 PRINCIPLES OF OPERATION The X9470 is a Bias Controller that contains all the necessary analog components for closed-loop DC bias control of LDMOS Transistors in RF Applications. The X9470 provides a mechanism to periodically set DC bias operating points of Class A or AB-type amplifiers to account for VGS drift and temperature variations. The following is an example of X9470 operation. The X9470 incorporates an instrumentation amplifier, comparator and buffer amplifier along with resistor arrays and their associated registers and counters. The serial interface provides direct communication between the host and the X9470. This section provides a detailed example of how the X9470 can be used to calibrate and dynamically set the optimum bias operating point of an RF power amplifier (see Figure 5): - State 0: Power-on Monitor Mode - State 1: DC-bias Setting When No RF is Present [Calibration] - State 2: Calibration Disable When RF is Present - State 3: PA Standby Mode. Dynamic Adjustment for VGS drift and Temperature variation - State 4: Power Off (Shutdown) Mode [Turn off the Power Amplifier]
State 0: Monitor Mode The VOUT and INC/DEC outputs of the X9470 can be used for monitoring and diagnostic purposes. Since VOUT has a lower gain (20x, default) than the internal IA output, it can handle higher drain sense current while keeping the output below the rail. This allows normal PA power monitoring, and over-current sensing using an external comparator. The INC/DEC pin can be monitored during calibration to see if there is no change, which indicates LDMOS functional problems. Note that the INC/DEC status is also available in the status register for software status reads. State 1: DC-bias Setting When No RF is Present [Calibration] At calibration, the DC bias operating point of the LDMOS Power Amplifier must be set. As soon as the Bias Adjustment Circuit Block is enabled (CS enabled, SDA high, and SCL pulse provided), the X9470 will automatically calibrate the external Power Amplifier by continually sampling the drain current of the external Power Amplifier and make adjustments to the gate voltage of the amplifier (See Figure 6).
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Figure 5. Operating modes X9470
State 0
PA Monitor Mode
PA Enabled, Vout and INC/DEC Monitored for status
State 1
PA Calibration Mode
Choose Vref to scale IDQ, perform calibration, Latch bias point for DC bias current in wiper counter
State 2
PA Transmit Mode
Disable Bias Adjustment,
State 3
PA Standby Mode
Recalibrate bias point for drift and temperature. Rbias resistor will automatically increment or decrement for optimal operating point continuously
State 4
PA Off Mode
Turn off PA
When no RF signal is present, the instrumentation amplifier of the X9470 senses the drain current as a voltage drop, V, across an external drain Rsense resistor. The V is amplified and compared to an external scaling voltage, VREF . Any difference between V and VREF results in a resistive increment or decrement of the internal RBIAS potentiometer. The RBIAS potentiometer is used as a voltage divider with the RHBIAS and RLBIAS terminals setting the upper and lower voltage limits of the unbuffered RWBIAS voltage. The resolution of the RBIAS potentiometer resistor is 0.4% of the difference of voltage across the RHBIAS and RLBIAS terminals. The RTOTAL is typically 10k with 256-taps. So, for example, if the difference between the RHBIAS and RLBIAS terminals is 1.024V, then the step accuracy is 4mV. The voltage at the RWBIAS pin is then fed into the VBIAS voltage follower. The VBIAS pin is a buffered output that is used to drive the gate of an LDMOS transistor. The scaling voltage, VREF, set by the RREF potentiometer, sets the calibrated operating point of the LDMOS Amplifier.
On edge transitions of the INC/DEC signal, the X9470 will latch the current wiper position - this is known as "Bias LockTM" mode. This is shown in Figure 6. When BiasLock occurs, the comparator hysteresis will allow INC/DEC to change state only after the IA output changes by more than 20mV. This will prevent toggling of the VBIAS output unless the drain bias current is constantly changing. State 2: DC-bias Disable When RF is Present (optional) When an RF signal is present, the X9470 is put into standby mode (open loop). The X9470 is in standby mode when the CS pin is disabled so that the RBIAS potentiometer holds the last wiper position. The presence of an RF signal at the input of a Class A or AB amplifier increases the current across the Rsense resistor. Over a period of time, the temperature of the LDMOS also increases and the LDMOS also experiences VGS drift. Therefore the DC biasing point that was set during State 1 (calibration) is not optimal. Adjustments to the gate voltage will need to be made to optimize the operation of the LDMOS PA. This is done in State 3.
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State 3: PA Standby Mode, DC Bias Adjustment [Compensation for VGS Drift and Temperature Variation] When the Power Amplifier is in Standby Mode the X9470 allows for dynamic adjustment of the DC biasing point to take into account both VGS drift and temperature variation. Dynamic biasing is achieved with the X9470 by using the CS, and SCL pins. For example, the SCL pin can be a steady clock and the CS pin can be used as a control signal to enable/disable the Bias Adjustment Block. Figure 6 illustrates how the X9470 can be used for dynamic biasing. Upon the presence of an RF signal, the CS pin is pulled LOW. This will prevent the X9470 from changing the VBIAS voltage during IDQ peak currents. Once the RF signal is no longer present, the CS pin can be enabled (closed loop), SDA high and the X9470 Bias Adjustment Circuit moves the VBIAS voltage (the gate voltage of the FET) to meet the average IDQ bias point for optimum amplifier performance. State 4: Power Off Mode During power saving or power-off modes the X9470 can be shut down via the SHDN pin. This pin pulls the output of the VBIAS pin LOW. Figure 6. Dynamic Biasing Technique: Automatic DC Bias Operating Point Adjustment
State 0 Monitor Mode RF signal
State 1 Calibration (no RF present)
State 2 RF present
State 3 Recalibrate bias point for drift and temperature
State 4 shut down
Set Operating Range Scale for Bias Adjustment VREF
Bias Adjustment ON CS
Bias Adjustment ON
Bias Adjustment OFF
SCL
INC/DEC
Saves wiper position to volatile memory
BiasLock
BiasLock
SHDN
6 VBIAS 3 Rbias default is zero point of Rtotal 1 Automatic Bias Adjustment 2 Latch Rbias DC point in calibration vs VREF RF present Turn off Bias Adjustment 4 Rbias increase/decrease after RF present due to temperature increase & VGS-threshold drift 5 IDQ vs. gate voltage bias optimized
Shut down
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X9470 STATUS REGISTER (SR) AND CONTROL REGISTER (CR) INFORMATION Table 2. Status Register (SR) Byte Addr
0F hex
SR7
SHDN
SR6
INC/DEC
SR5
0
SR4
CS
SR3
0
SR2
0
SR1
WEL
SR0
Gain
STATUS REGISTER (SR) The Status Register is located at address 0F. This is a register used to control the write enable latches, and monitor status of the SHDN, INC/DEC, and CS pin. This register is separate from the Control Register. SR7: SHDN: Vbias SHDN Flag. Read Only--Volatile. The bit keeps status of the shutdown pin, SHDN. When this bit is HIGH, the SHDN pin is active and the VBIAS output is disabled. When this bit is LOW, the SHDN pin is low and VBIAS output is enabled. SR6: INC/DEC : Read Only--Volatile. This bit keeps status of the INC/DEC pin. When this bit is HIGH the counter is in increment mode, when this bit is LOW the counter is in decrement mode. SR4: CS: Read Only--Volatile. This bit keeps status on the CS pin. When this bit is HIGH, the X9470 is in closed loop mode (Rbias adjustment enabled). When this bit is LOW the x9470 is in open loop mode (no Rbias adjustments). SR2, SR3, SR5: Read only For internal test usage, should be set to 0 during SR writes. Table 3. Control Registers (CR) Byte Addr.
00 hex 01 hex
Note:
SR1: WEL: Write Enable Latch--Volatile The WEL bit controls the access to the registers during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is set LOW, Nonvolatile writes to the registers will be ignored, and all writes to registers will be volatile. The WEL bit is set by writing a "1" to the WEL bit and zeroes to the other bits of the Status Register. Once this write operation is completed and a STOP command is issued, nonvolatile writes will then occur for all NOVRAM registers and control bits. Once set, the, WEL bit remains set until either reset to 0 (by writing a "0" to the WEL bit and zeroes to the other bits of the Status Register) or until the part powers up again. SR0: Gain - NOVRAM Selects VOUT and IA gain. When SR0=0, VOUT gain = 20x, IA gain = 50x. When SR0 = 1, VOUT gain = 50x, and IA gain = 20x. Default setting is 0. CONTROL REGISTERS (CR) The control registers are organized for byte operations. Each byte has a unique byte address as shown in Table 3 below.
Bit Description
DCP for Vbias DCP for VREF
Reg Name
Vbias Vref
7
Vb7 X
6
Vb6 X
5
Vb5 Vr5
4
Vb4 Vr4
3
Vb3 Vr3
2
Vb2 Vr2
1
Vb1 Vr1
0
Vb0 Vr0
Memory Type
NOVRAM NOVRAM
02H to 0EH are reserved for internal manufacturing use.
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X9470 BUS INTERFACE INFORMATION Figure 7. Slave Address, Word Address, and Data Bytes - Write Mode
Device Identifier Slave Address
Slave Address Byte 0 1 0 1 S2 S1 S0 R/W=0 Byte 0
Byte Address A7 A6 A5 A4 A3 A2 A1 A0 Byte 1
0Fh : SR 00h : VBIAS 01h : VREF
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte Byte 2
Figure 8. Slave Address, Word Address, and Data Bytes - Read Mode
Device Identifier Slave Address
Slave Address Byte 0 1 0 1 S2 S1 S0 R/W Byte 0
Data Byte D7 D6 D5 D4 D3 D2 D1 D0 Byte 1
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte Byte 2
Slave Address, Byte Address, and Data Byte The byte communication format for the serial bus is shown in Figures 7 and 8 above. The first byte, BYTE 0, defines the device indentifier, 0101 in the upper half; and the device slave address in the low half of the byte. The slave address is determined by the logic values of the A0, A1, and A2 pins of the X9470. This allows for up to 8 unique addresses for the X9470. The next byte, BYTE 1, is the Byte Address. The Byte Address identifies a unique address for the Status or Control Registers as shown in Table 3. The following byte, Byte 2, is the data byte that is used for READ and WRITE operations.
Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 9.
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Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 9. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 10. Figure 9. Valid Start and Stop Conditions The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for: - The Slave Address Byte when the Device Identifier and/or Select bits are incorrect - The 2nd Data Byte of a Status Register Write Operation (only 1 data byte is allowed)
SCL
SDA Start Stop
Figure 10. Acknowledge Response From Receiver
SCL from Master Data Output from Transmitter Data Output from Receiver Start Acknowledge
1
8
9
Figure 11. Valid Data Changes on the SDA Bus
SCL
SDA Data Stable Data Change Data Stable
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WRITE OPERATIONS Byte Write For a write operation, the device requires the Slave Address Byte and the Word Address Bytes. This gives the master access to any one of the words in the array. Upon receipt of each address byte, the X9470 responds with an acknowledge. After receiving the address bytes the X9470 awaits the eight bits of data. After receiving the 8 data bits, the X9470 again responds with an acknowledge. The master then terminates the transfer by generating a stop condition. The X9470 then begins an internal write cycle of the data to the nonvolatile memory. During the internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 12. A write to a protected block of memory is ignored, but will still receive an acknowledge. At the end of the write command, the X9470 will not initiate an internal write cycle, and will continue to ACK commands. Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and it's associated ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte + ACK is sent, then the X9470 resets itself without performing the write. The contents of the array are not affected. Acknowledge Polling Disabling of the inputs during nonvolatile write cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master's byte load operation, the X9470 initiates the internal nonvolatile write cycle. Acknowledge polling can begin immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the X9470 is still busy with the nonvolatile write cycle then no ACK will be returned. When the X9470 has completed the write operation, an ACK is returned and the host can proceed with the read or write operation. Refer to the flow chart in Figure 15. READ OPERATIONS There are three basic read operations: Current Address Read, Random Read, and Sequential Read. Current Address Read Internally the X9470 contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power-up, the address is initialized to 0h. In this way, a current address read immediately after the power-on reset can download the entire contents of memory starting at the first location. Upon receipt of the Slave Address Byte with the R/W bit set to one, the X9470 issues an acknowledge, then transmits eight data bits. The master terminates the read operation by not responding with an acknowledge during the ninth clock and issuing a stop condition. Refer to Figure 13 for the address, acknowledge, and data transfer sequence.
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Figure 12. Byte Write Sequence
S t Device a ID r t
Signals from the Master
Slave Address
Byte Address 0
Data
S t o p
SDA Bus Signals From The Slave
0 1 0 1 A2 A1 A0 0 A C K A C K A C K
Figure 13. Current Address Read Sequence
S t Device a ID r t
Signals from the Master
Slave Address
S t o p
SDA Bus Signals from the Slave
0 1 0 1 A2 A1 A0 1 A C K Data A C K
Figure 14. Random Address Read Sequence
Signals from the Master
S t Device a ID r t
Slave Address
Byte Address 0
S t Device a ID r t
Slave Address
S t o p
SDA Bus Signals from the Slave
0 1 0 1 A2 A1 A0 0 A C K A C K
0 1 0 1 A2 A1 A0 1 A C K Data A C K
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Figure 15. Acknowledge Polling Sequence Random Read Random read operations allows the master to access any location in the X9470. Prior to issuing the Slave Address Byte with the R/W bit set to zero, the master must first perform a "dummy" write operation. The master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. After acknowledging receipt of each word address byte, the master immediately issues another start condition and the slave address byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit data word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. Refer to Figure 13 for the address, acknowledge, and data transfer sequence. In a similar operation called "Set Current Address," the device sets the address if a stop is issued instead of the second start shown in Figure 14. The X9470 then goes into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter. The next Current Address Read operation will read from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data.
Byte load completed by issuing STOP. Enter ACK Polling
Issue START
Issue Slave Address Byte (Read or Write) NO
Issue STOP
ACK returned? YES nonvolatile write Cycle complete. Continue command sequence? YES Continue normal Read or Write command sequence
NO Issue STOP
PROCEED
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.
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PACKAGING INFORMATION 24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.303 (7.70) .311 (7.90)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.06) .005 (.15)
.010 (.25) Gage Plane 0 - 8 .020 (.50) .030 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 24
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